The present invention relates to a pulse train divider circuit comprising first and second D-type flip-flops having the Q output of the first flip-flop connected to the D input of the second flip-flop whose Q output is connected to the D input of the first flip-flop, the pulse train to be divided being applied to the clock inputs of each of said flip-flops.
A divider circuit of the above type is disclosed in Electronic Letters, volume 18, number 13, dated June 24, 1982, at page 581. This reference shows two D-type flip-flops connected and driven to produce divide-by-four outputs of fixed phase relationship.